1. Field of the Invention
The present invention relates to a clock generator circuit for generating two pairs of clock signals by using a reference clock signal.
As the case may require, four clock signals, that is, two pairs of clock signals are used. For example, such clock signals are used in a switched cpacitor integrator. In this case, it is necessary that a pair of clock signals opposite in phase to each other are not overlapped with another pair of clock signals opposite in phase to each other.
2. Description of the Prior Art
One conventional clock generator circuit comprises a pair of NOR circuits cross-coupled to each other, which serve as an R-S flip-flop. This clock generator circuit generates two non-overlapping clock signals .phi..sub.1 and .phi..sub.2 opposite in phase to each other. (See: Electronics, page 99, Jan. 20, 1977.) In this circuit, when an inverter is connected to the output terminal of each of the NOR circuits, two inverted clock signals .phi..sub.1 and .phi..sub.2 of the clock signals .phi..sub.1 and .phi..sub.2 are also obtained. Thus, the clock generator circuit associated with such inverters generates two pairs of clock signals .phi..sub.1 and .phi..sub.1, and .phi..sub.2 and .phi..sub.2.
However, in the above-mentioned circuit, due to fluctuation in manufacture, the delay time of each of the inverters is fluctuated. At worst, this delay time is so long that the clock signal .phi..sub.1 may be overlapped with the clock signals .phi..sub.2 and .phi..sub.2 and in addition, the clock signal .phi..sub.2 may be overlapped with the clock signal .phi..sub.1 and .phi..sub.1.